In this paper, we propose an efficient architecture based on pre-computation for Viterbi decoders incorporating T-algorithm. Through optimization at both. A Fast ACSU Architecture for Viterbi Decoder Using T-Algorithm. Jinjin He, Huaping Liu, Senior Member, IEEE, and Zhongfeng Wang*, Senior Member, IEEE. High performance ACS for Viterbi decoder using pipeline T-Algorithm .. Z. Wang, A fast ACSU architecture for Viterbi decoder using T-Algorithm, in: Proc.

Author: Targ Bajinn
Country: Estonia
Language: English (Spanish)
Genre: Personal Growth
Published (Last): 20 January 2010
Pages: 44
PDF File Size: 6.71 Mb
ePub File Size: 17.51 Mb
ISBN: 865-1-40927-600-2
Downloads: 46215
Price: Free* [*Free Regsitration Required]
Uploader: Goltisar

Also, we assume that each remaining metric would cause a computational overhead of one addition operation. Finally, we presented a design case. Showing of 20 extracted citations.

So, In terms of power consumption, the viterbi decoder is dominant module in a TCM decoder. Again, to simplify the evaluation, we consider, a code with a constraint length k and q precomputation steps.

Low power Viterbi decoder for Trellis coded

Showing of 6 references. This paper has 27 citations.

Basically M-Algorithm requires a sorting process in a feedback loop where as T— Algorithm only searches for the optimal path metric [P] that is the maximum value or the minimum value of Ps. In order to reduce the computational complexity as well as power consumption, low power schemes should be exploited for the VD in a TCM decoder.

We again need to analyze the trellis transition of the original code. The Branch metric can be calculated by two types: We have also analyzed the precomputation algorithm, where the optimal precomputation steps are calculated and discussed. Therefore, a straight forward implementation of T- Algorithm will wcsu reduce the decoding speed.

Compared with the SEPC-T algorithm, however, the critical fasr of the 1-sept pre-computation scheme is still long[12]. This architecture has been optimized to meet the iteration bound [9]. Therefore, to maintain a good BER performance, the minimum threshold we chose is 0.


In his section, we further address the SMU design issue. Com-pared with the conventional T-algorithm, the computational overhead of this architecture is 12 addition operations and a comparison, which is slightly more than the number obtained from the evaluation in 5. Even if the extra delay is hard to eliminate, the resultant clock speed is very close to the theoretical bound. Article Tools Print this article. In the 1-step pre-computation architecture, we have pointed out that for the particular code shown in Fig.

Viterbi Convolutional Encoding and Viterbi Decoding. Implementation of such a table is not trivial. Trellis coded modulation schemes are used in many bandwidth efficient systems. The BMs are categorized in the same way and are described by 8.

There was a problem providing the content you requested

Breadth-first trellis decoding with adaptive effort Stanley J. The functional block diagram of viterbi decoder with two step precomputation T-algorithm is shown in fig.

NSP, digital communications by satellite. The trellis butterflies for a VD usually have a symmetric structure. Hamming distance and Euclidean distance [10]. The 64 states and path metrics are labeled from 0 to Over scaling of the supply voltage is having a problem that it needs to take whole system into consideration including with VD at which we are not focusing of architechure research.

It is clear that the conventional T- algorithm is not suitable for high-speed applications. Archtecture a TCM system employs a high rate convolutional code, which leads to high complexity of viterbi decoder for the TCM decoder, when the eecoder length of Convolutional code is also normal.

Also, any kinds of low-power scheme would introduce extra hardware like the purge acxu shown in Fig. It is essential to use T-algorithm in Viterbi decoders to prune significant portions of the trellis states to dramatically reduce power consumption. The key point of improving the clock speed of T-Algorithm is to quickly find the decoer path metric. In order to further shorten the critical path, we explore the 2-step pre-computation design next. The functional diagram of the 1-step pre-computation scheme is shown in Fig.


Therefore, it is worth to discuss the optimal number of precomputation steps. Abdul SubhanDikpal Reddy The decrease of clock speed is inevitable since the iteration bound for VD with T -algorithm is inherently longer than that of the full-trellis VD. The Basic idea of the precomputation algorithm was presented in [9].

Low power Viterbi decoder for Trellis coded Modulation using T-algorithm

X 1 0 ………………………. It is well known that viterbi decoder is dominant module for finding the overall power consumption for the TCM decoders. T-Algorithm has been shown to very efficient in reducing the power consumption [7],[8]. The synthesis targets to achieve the maximum clock speed for each case and the results are shown in Table III. Computational overhead compared with conventional T-algorithm is an important factor that should be carefully evaluated.

Power reduction in VDs could be achieved by reducing the number of states, for example reduced state sequence decoding [3], M- algorithm [4] and T-algorithm [1],[5], or by over scaling the. IC design of an adaptive Viterbi decoder.

Very Large Scale Integr. On the other hand, the VD with conventional T- algorithm cannot achieve half of the clock speed of the full trellis VD.